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| 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A SST31LF041 / 041A4Mb Flash (x8) + 1 Mb SRAM (x8) ComboMemories Data Sheet FEATURES: * Monolithic Flash + SRAM ComboMemory - SST31LF041/041A: 512K x8 Flash + 128K x8 SRAM - SST31LF043/043A: 512K x8 Flash + 32K x8 SRAM * Single 3.0-3.6V Read and Write Operations * Concurrent Operation - Read from or write to SRAM while Erase/Program Flash * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 10 mA (typical) for Flash and 20 mA (typical) for SRAM Read - Standby Current: 10 A (typical) * Flash Sector-Erase Capability - Uniform 4 KByte sectors * Latched Address and Data for Flash * Fast Read Access Times: - SST31LF041/043 Flash: 70 ns SRAM: 70 ns - SST31LF041A/043A Flash: 300 ns SRAM: 300 ns * Flash Fast Erase and Byte-Program: - Sector-Erase Time: 18 ms (typical) - Bank-Erase Time: 70 ms (typical) - Byte-Program Time: 14 s (typical) - Bank Rewrite Time: 8 seconds (typical) * Flash Automatic Erase and Program Timing - Internal VPP Generation * Flash End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard Command Set * Packages Available - 32-lead TSOP (8 x 14 mm) SST31LF041A/043A - 40-lead TSOP (10 x 14 mm) SST31LF041/043 PRODUCT DESCRIPTION The SST31LF041/041A/043/043A devices are a 512K x8 CMOS flash memory bank combined with a 128K x8 or 32K x8 CMOS SRAM memory bank manufactured with SST's proprietary, high performance SuperFlash technology. The SST31LF041/041A/043/043A devices write (SRAM or flash) with a 3.0-3.6V power supply. The monolithic SST31LF041/041A/043/043A devices conform to Software Data Protect (SDP) commands for x8 EEPROMs. Featuring high performance Byte-Program, the flash memory bank provides a maximum Byte-Program time of 20 sec. The entire flash memory bank can be erased and programmed byte-by-byte in typically 8 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST31LF041/041A/ 043/043A devices have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST31LF041/041A/043/043A devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST31LF041/041A/043/043A operate as two independent memory banks with respective bank enable signals. The SRAM and Flash memory banks are superimposed in the same memory address space. Both (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 1 memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the SRAM bank and the flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST31LF041/041A/043/043A provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs SectorErase, Bank-Erase, or Byte-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write. The SST31LF041/041A/043/043A devices are suited for applications that use both nonvolatile flash memory and volatile SRAM memory to store code or data. For all system applications, the SST31LF041/041A/043/043A The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet devices significantly improve performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST31LF041/041A/043/043A inherently use less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter Erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The monolithic ComboMemory eliminates redundant functions when using two separate memories of similar architecture; therefore, reducing the total power consumption. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST31LF041/041A/043/043A devices also improve flexibility by using a single package and a common set of signals to perform functions previously requiring two separate devices. To meet high density, surface mount requirements, the SST31LF041/043 device is offered in 40-lead TSOP package and the SST31LF041A/043A device is offered in 32-lead TSOP package. See Figures 1 and 2 for the pinouts. SRAM Operation With BES# low and BEF# high, the SST31LF041/041A operate as a 128K x8 CMOS SRAM and the SST31LF043/043A operate as 32K x8 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SRAM is mapped into the first 128 KByte address space of the device for 041/041A or 32 KByte for 043/043A. Read and Write cycle times are equal. SRAM Read The SRAM Read operation of the SST31LF041/041A/ 043/043A are controlled by OE# and BES#, both have to be low with WE# high, for the system to obtain data from the outputs. BES# is used for SRAM bank selection. When BES# and BEF# are high, both memory banks are deselected. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 3 for the Read cycle timing diagram. SRAM Write The SRAM Write operation of the SST31LF041/041A/043/ 043A is controlled by WE# and BES#; both have to be low for the system to write to the SRAM. BES# is used for SRAM bank selection. During the Byte-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE#, whichever occurs first. The Write time is measured from the last falling edge to the first rising edge of BES# and WE#. OE# can be VIL or VIH, but no other value, for SRAM Write operations. See Figure 4 for the SRAM Write cycle timing diagram. Device Operation The ComboMemory uses BES# and BEF# to control operation of either the SRAM or the flash memory bank. Bus contention is eliminated as the monolithic device will not recognize both bank enables as being simultaneously active. If both bank enables are asserted (i.e., BEF# and BES# are both low), the BEF# will dominate while the BES# is ignored and the appropriate operation will be executed in the flash memory bank. SST does not recommend that both bank enables be simultaneously asserted. All other address, data, and control lines are shared which minimizes power consumption and area. The device goes into standby when both bank enables are raised to VIHC. See Table 3 for SRAM operation mode selection. For SST31LF041A/043A only: BES# and OE# share pin 32. During SRAM operation, pin 32 will function as BES#. During flash operation, pin 32 will function as OE#. When pin 32 (OE#/BES#) is high, the data bus is in high impedance state. Flash Operation With BEF# active, the SST31LF041/041A/043/043A operate as a 512K x8 flash memory. The flash memory bank is read using the common address lines, data lines, WE# and OE#. Erase and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are latched during the SDP commands and internally timed Erase and Program operations. See Table 3 for flash operation mode selection. Flash Read The Read operation of the SST31LF041/041A/043/043A devices are controlled by BEF# and OE#; both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# and BES# are high, both banks are deselected and only standby power is consumed. OE# is the (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 2 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 5 for the Read cycle timing diagram. using either Data# Polling or Toggle Bit methods. See Figure 10 for timing waveforms. Any SDP commands loaded during the Sector-Erase operation will be ignored. Flash Erase/Program Operation SDP commands are used to initiate the flash memory bank Program and Erase operations of the SST31LF041/041A/ 043/043A. SDP commands are loaded to the flash memory bank using standard microprocessor write sequences. A command is loaded by asserting WE# low while keeping BEF# low and OE# high. The address is latched on the falling edge of WE# or BEF#, whichever occurs last. The data is latched on the rising edge of WE# or BEF#, whichever occurs first. Flash Bank-Erase Operation The SST31LF041/041A/043/043A flash memory bank provides a Bank-Erase operation, which allows the user to erase the entire flash memory bank array to the "1s" state. This is useful when the entire bank must be quickly erased. The Bank-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Bank-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or BEF# pulse, whichever occurs first. During the internal Erase operation, the only valid Flash Read operations are Toggle Bit and Data# Polling. See Table 4 for the command sequence, Figure 11 for timing diagram, and Figure 20 for the flowchart. Any SDP commands loaded during the Bank-Erase operation will be ignored. Flash Byte-Program Operation The flash memory bank of the SST31LF041/041A/043/ 043A devices are programmed on a byte-by-byte basis. Before the Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 s. See Figures 6 and 7 for WE# and BEF# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid Flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored. Flash Write Operation Status Detection The SST31LF041/041A/043/043A flash memory bank provides two software means to detect the completion of a flash memory bank Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit Read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Flash Sector-Erase Operation The Sector-Erase operation allows the system to erase the flash memory bank on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KBytes. The Sector-Erase operation is initiated by executing a sixbyte-command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A18-A12 will be used to determine the sector address. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined (c)2001 Silicon Storage Technology, Inc. Flash Data# Polling (DQ7) When the SST31LF041/041A/043/043A flash memory bank is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The flash memory bank is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of the fourth WE# S71107-03-000 5/01 349 3 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet (or BEF#) pulse for Program operation. For Sector or BankErase, the Data# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 18 for a flowchart. Concurrent Read and Write Operations The SST31LF041/041A/043/043A provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the Flash. The device will ignore all SDP commands when an Erase or Program operation is in progress. This allows data alteration code to be executed from SRAM, while altering the data in Flash. The following table lists all valid states. SST does not recommend that both bank enables, BEF# and BES#, be simultaneously asserted. CONCURRENT READ/WRITE STATE TABLE Flash Program/Erase Program/Erase SRAM Read Write Flash Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The flash memory bank is then ready for the next operation. The Toggle Bit is valid after the rising edge of the fourth WE# (or BE#) pulse for Program operation. For Sector or Bank-Erase, the Toggle Bit is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 9 for Toggle Bit timing diagram and Figure 18 for a flowchart. Flash Memory Data Protection The SST31LF041/041A/043/043A flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. Product Identification The product identification mode identifies the devices as either SST31LF041/043 or SST31LF041A/043A and the manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware device ID Read operation is typically used by a programmer to identify the correct algorithm for the SST31LF041/041A/043/ 043A flash memory banks. Users may wish to use the software product identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 12 for the software ID entry and read timing diagram and Figure 19 for the ID entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION Address Manufacturer's ID Device ID SST31LF041 SST31LF041A SST31LF043 SST31LF043A 0001H 0001H 0001H 0001H 17H 16H 65H 66H T1.2 349 Flash Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Flash Write operation. This prevents inadvertent writes during power-up or power-down. Flash Software Data Protection (SDP) The SST31LF041/041A/043/043A provide the JEDEC approved Software Data Protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST31LF041/041A/043/043A devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid SDP commands will abort the device to the Read mode, within TRC. Data BFH 0000H Product Identification Mode Exit/Reset In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 4 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet which returns the device to the Read operation. Please note that the software-reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform and Figure 19 for a flowchart. Design Considerations SST recommends a high frequency 0.1 F ceramic capacitor to be placed as close as possible between VDD and VSS, e.g., less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 F electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. FUNCTIONAL BLOCK DIAGRAM Address Buffers SRAM AMS - A0 BES# BEF# OE# WE# Control Logic I/O Buffers DQ7 - DQ0 Address Buffers & Latches SuperFlash Memory 349 ILL B1.6 AMS = Most Significant Address A16 A15 A14 A13 A12 A11 A9 A8 WE# NC BES# NC A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Standard Pinout Top View Die Up 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 VSS NC NC A10 DQ7 DQ6 DQ5 DQ4 VDD VDD NC DQ3 DQ2 DQ1 DQ0 OE# VSS BEF# A0 349 ILL F01.2 FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP (10MM X 14MM) - SSTLF041/043 (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 5 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View Die Up 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE#/BES# A10 BEF# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 349 ILL F01A.1 FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM TABLE 2: PIN DESCRIPTION Symbol AMS1-A0 Pin Name Address Inputs Functions X 14MM) - SSTLF041A/043A To provide memory addresses. A18-A0 to provide flash address A16-A0 to provide SRAM addresses for SST32LF041/041A A14-A0 to provide SRAM addresses for SST31LF043/043A During flash Sector-Erase, A18-A12 address lines will select the sector. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# or BES# and BEF# are high. DQ7-DQ0 Data Input/output BES# BEF# OE# WE# VDD VSS SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low. Note: For SST31LF041A/043A, BES# and OE# share pin 32. Flash Memory Bank Enable Output Enable Write Enable Power Supply Ground T2.11 349 To activate the Flash memory bank when BEF# is low. To gate the data output buffers. Note: For SST31LF041A/043A, BES# and OE# share pin 32. To control the Write operations. 3.0-3.6V Power Supply 1. AMS = Most significant address (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 6 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet TABLE 3: OPERATION MODES SELECTION Mode Flash Read Program Erase SRAM Read Write Standby Flash Write Inhibit VIL VIL VIHC X X X Product Identification Hardware Mode Software Mode X X VIL VIL VIL VIL VIH VIH VH AIN Manufacturer's ID (BFH) Device ID3 ID Code A18-A1=VIL, A0=VIL A18-A1=VIL, A0=VIH See Table 4 T3.9 349 BES#1 X2 X X BEF#1 VIL VIL VIL OE# VIL VIH VIH WE# VIH VIL VIL A9 AIN AIN X DQ DOUT DIN X Address AIN AIN Sector address, XXH for Bank-Erase AIN AIN X X X X VIH VIH VIHC X X VIH VIL X X VIL X X VIH VIL X X VIH X AIN AIN X X X X DOUT DIN High Z High Z / DOUT High Z / DOUT High Z / DOUT 1. BES# and BEF# cannot be asserted simultaneously. For SST31LF041A/043A BES# and OE# share pin 32. When flash is active, pin 32 becomes OE#. When flash is inactive, pin 32 becomes BES#. 2. X can be VIL or VIH, but no other value. 3. Device ID 17H for SST31LF041, 16H for SST31LF041A, 65H for SST31LF043 and 66H for SST31LF043A. TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence Byte-Program Sector-Erase Bank-Erase Software ID Entry4,5 Software ID Exit 1. 2. 3. 4. 5. 1st Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H Data AAH AAH AAH AAH AAH 2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data 55H 55H 55H 55H 55H 3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H Data A0H 80H 80H 90H F0H 4th Bus Write Cycle Addr1 BA2 5555H 5555H Data Data AAH AAH 5th Bus Write Cycle Addr1 2AAAH 2AAAH Data 55H 55H 6th Bus Write Cycle Addr1 SAX3 5555H Data 30H 10H T4.7 349 Address format A14-A0 (Hex),Address A15-A18 can be VIL or VIH, but no other value, for the Command sequence. BA = Program Byte address SAX for Sector-Erase; uses A18-A12 address lines The device does not remain in Software Product ID Mode if powered down. With A18-A1 =0; SST Manufacturer's ID= BFH, is read with A0 = 0, SST31LF041 Device ID = 17H, is read with A0 = 1, SST31LF041A Device ID = 16H, is read with A0 = 1 SST31LF043 Device ID = 65H, is read with A0 = 1 SST31LF043A Device ID = 66H, is read with A0 = 1 (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 7 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Commercial Extended Ambient Temp 0C to +70C -20C to +85C VDD 3.0-3.6V 3.0-3.6V AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 15 and 16 (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 8 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet TABLE 5: DC OPERATING CHARACTERISTICS (VDD = 3.0-3.6V) Limits Symbol IDD Parameter Power Supply Current Read Flash SRAM Concurrent Operation Write Flash (Program) SRAM ISB ILI ILO VIL VIH VIHC VOL VOH VH IH 1 Min Max Units Test Conditions Address input = VIL/VIH, at f=1/TRC Min, VDD=VDD Max, all DQs open 12 40 55 15 40 30 1 1 0.4 0.7VDD VDD-0.3 0.2 VDD-0.2 11.4 12.6 200 mA mA mA mA mA A A A V V V V V V A OE#=VIL, WE#=VIH BEF#=VIL, BES#=VIH BEF#=VIH, BES#=VIL BEF#=VIH, BES#=VIL OE#=VIH, WE#=VIL BEF#=VIL, BES#=VIH BEF#=VIH, BES#=VIL BEF#=BES#=VIHC, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD = VDD Min VDD = VDD Max VDD = VDD Max IOL = 100 A, VDD = VDD Min IOH = -100 A, VDD = VDD Min BEF#=OE#=VIL, WE#=VIH BEF#=OE#=VIL, WE#=VIH, A9=VH Max T5.14 349 Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage Supervoltage for A9 pin Supervoltage Current for A9 pin 1. Specification applies to commercial temperature devices only. This parameter may be higher for extended devices. TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ 1 Parameter Power-up to Read Operation Power-up to Write Operation Minimum 100 100 Units s s T6.2 349 TPU-WRITE1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7: CAPACITANCE Parameter CI/O1 CIN 1 (Ta = 25C, f=1 Mhz, other pins open) Description I/O Pin Capacitance Input Capacitance Test Condition VI/O = 0V VIN = 0V Maximum 12 pF 6 pF T7.2 349 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: RELIABILITY CHARACTERISTICS Symbol NEND TDR1 ILTH1 1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78 T8.4 349 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 9 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet AC CHARACTERISTICS TABLE 9: SRAM MEMORY BANK CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) SST31LF041/043-70 Symbol TRCS TBES TAAS TOES1 TBLZS2 TOLZS1 TBHZS1 TOHZS1 TOHS Parameter Read Cycle Time Bank Enable Access Time Address Access Time Output Enable Access Time BES# to Active Output Output Enable to Active Output BES# to High-Z Output Output Disable to High-Z Output Output Hold from Address Change 0 0 0 25 25 10 Min 70 70 70 35 0 0 30 30 Max SST31LF041A/043A-300 Min 300 300 300 150 Max Units ns ns ns ns ns ns ns ns ns T9.8 349 1. No TOES value for SST31LF041A/043A 2. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: SRAM MEMORY BANK WRITE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) SST31LF041/043-70 Symbol TWCS TBWS TAWS TASTS TWPS TWRS TDSS TDHS Parameter Write Cycle Time Bank Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Set-up Time Data Hold from Write Time Min 70 60 60 0 60 0 30 0 Max SST31LF041A/043A-300 Min 300 230 230 0 200 0 150 0 Max Unit ns ns ns ns ns ns ns ns T10.5 349 TABLE 11: FLASH READ CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) SST31LF041/043-70 Symbol TRC TBE TAA TOE TBLZ1 TOLZ1 TBHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Bank Enable Access Time Address Access Time Output Enable Access Time BEF# Low to Active Output OE# Low to Active Output BEF# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 0 0 0 15 15 0 Min 70 70 70 40 0 0 60 60 Max SST31LF041A/043A-300 Min 300 300 300 150 Max Units ns ns ns ns ns ns ns ns ns T11.5 349 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 10 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) SST31LF041/043-70 Symbol TBP TAS TAH TBS TBH TOES TOEH TBP TWP TWPH TBPH TDS TDH TIDA TSE TSBE TBS Parameter Byte-Program Time Address Setup Time Address Hold Time WE# and BEF# Setup Time WE# and BEF# Hold Time OE# High Setup Time OE# High Hold Time BEF# Pulse Width WE# Pulse Width WE# Pulse Width High BEF# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Bank-Erase Bank Enable Setup Time for Concurrent Operation 0 0 30 0 0 0 10 40 40 30 30 40 0 150 25 100 0 Min Max 20 0 50 0 0 0 10 100 100 50 50 50 0 150 25 100 SST31LF041A/ 043A-300 Min Max 20 Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns T12.4 349 (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 11 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet TRCS ADDRESS A16-0 TAAS BEF# BES# 1 TBES OE# 1 TOES TOHZS VIH WE# TOLZS DQ7-0 HIGH-Z TBLZS TOHS DATA VALID TBHZS HIGH-Z DATA VALID 349 ILL F02.9 Note 1: For SST31LF041A/043A. BES# and OE# share pin 32. During SRAM operation, pin 32 functions as BES#. FIGURE 3: SRAM READ CYCLE TIMING DIAGRAM TWCS ADDRESS A16-0 ADDRESS BEF# TBWS BES# 1 TAWS OE# 1 TWPS WE# TASTS TDSS DQ7-0 DATA VALID TWRS TDHS Note 1: For SST31LF041A/043A. BES# and OE# share pin 32. During SRAM operation, pin 32 functions as BES#. 349 ILL F03.10 FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 12 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet TRC ADDRESS A18-0 TAA BES#1 TBE BEF# OE#1 TOLZ VIH WE# TOE TOHZ DQ7-0 HIGH-Z TBLZ TOH DATA VALID TBHZ HIGH-Z DATA VALID 349 ILL F18.5 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 5: FLASH READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS A18-0 5555 TAH TWP WE# TAS OE#1 TWPH TDS 2AAA 5555 ADDR TDH BES#1 TCH BEF# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) 349 ILL F04.6 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 6: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 13 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS A18-0 BES#1 TAH TCP BEF# TAS OE# 1 5555 2AAA 5555 ADDR TDH TCPH TDS TCH WE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) 349 ILL F05.6 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 7: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM ADDRESS A18-0 BES# 1 TCE BEF# TOEH OE# 1 TOES TOE WE# DQ7 D D# D# D 349 ILL F06.6 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 8: FLASH DATA# POLLING TIMING DIAGRAM (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 14 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet ADDRESS A18-0 BES# 1 TBE BEF# TOEH OE# 1 TOE TOES WE# DQ6 TWO READ CYCLES WITH SAME OUTPUTS 349 ILL F07.6 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 9: FLASH TOGGLE BIT TIMING DIAGRAM SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A18-0 BES# 1 TSE SAX 5555 2AAA 5555 5555 2AAA BEF# OE#1 TWP WE# DQ7-0 AA SW0 Note: 55 SW1 80 SW2 AA SW3 55 SW4 30 SW5 349 ILL F08.8 The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 12) SAX = Sector Address Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 10: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 15 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet SIX-BYTE CODE FOR BANK-ERASE ADDRESS A18-0 BES#1 5555 2AAA 5555 5555 2AAA 5555 TSBE BEF# OE#1 TWP WE# DQ7-0 AA SW0 Note: 55 SW1 80 SW2 AA SW3 55 SW4 10 SW5 349 ILL F17.8 The device also supports BEF# controlled Bank-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 12) Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 11: WE# CONTROLLED FLASH BANK-ERASE TIMING DIAGRAM THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS A14-0 BES# 1 5555 2AAA 5555 0000 0001 BEF# OE#1 TIDA TWP WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2 TAA BF Device ID 349 ILL F09.7 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. Note: Device ID = 16H for SST31LF041A, 17H for SST31LF041, 65H for SST31LF043 and 66H for SST31LF043A. FIGURE 12: FLASH SOFTWARE ID ENTRY (c)2001 Silicon Storage Technology, Inc. AND READ S71107-03-000 5/01 349 16 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 BES#1 5555 2AAA 5555 DQ7-0 AA 55 F0 TIDA BEF# OE# 1 TWP WE# T WHP SW0 SW1 SW2 349 ILL F10.7 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 13: FLASH SOFTWARE ID EXIT AND RESET ADDRESS A18-0 BEj# TBS BEj1# WE# OE# DQ7-0 349 ILL F22.0 Note: j = F or S j1 = S or F FIGURE 14: TIMING DIAGRAM FOR ALTERNATING BETWEEN FLASH/SRAM AND SRAM/FLASH (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 17 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 349 ILL F11.1 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 15: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 349 ILL F12.2 FIGURE 16: A TEST LOAD EXAMPLE (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 18 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 349 ILL F13.2 FIGURE 17: BYTE-PROGRAM ALGORITHM (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 19 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet Internal Timer Byte Program/Erase Initiated Toggle Bit Byte Program/Erase Initiated Data# Polling Byte Program/Erase Initiated Wait TBP, TSBE, or TSE Read byte Read DQ7 Program/Erase Completed Read same byte No Is DQ7 = true data? Yes No Does DQ6 match? Yes Program/Erase Completed Program/Erase Completed 349 ILL F14.0 FIGURE 18: WAIT OPTIONS (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 20 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: F0H Address: XXH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Wait TIDA Load data: 90H Address: 5555H Load data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 349 ILL F15.2 FIGURE 19: SOFTWARE PRODUCT COMMAND FLOWCHARTS (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 21 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet Chip-Erase Command Sequence Load data: AAH Address: 5555H Sector-Erase Command Sequence Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 80H Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H Load data: 30H Address: SAX Wait TSBE Wait TSE Chip erased to FFH Sector erased to FFH 349 ILL F16.2 FIGURE 20: ERASE COMMAND SEQUENCE (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 22 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet Device Speed Suffix1 XX Suffix2 XX Package Modifier H = 32 leads I = 40 leads Numeric = Die modifier Package Type W = TSOP (8mm x 14mm - 32-lead package) (10mm x 14mm - 40-lead package) Temperature Range C = Commercial = 0C to +70C E = Extended = -20C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns 300 = 300 ns Version A = 32-lead TSOP Package Density 041/041A = 4 Mbit Flash + 1 Mbit SRAM 043/043A = 4 Mbit Flash + 256 Kbit SRAM Voltage L = 3.0-3.6V Device Family 31 = Monolithic ComboMemory SST31LF04xx - XXX SST31LF041 Valid combinations SST31LF041-70-4C-WI SST31LF041-70-4E-WI SST31LF041A Valid combinations SST31LF041A-300-4C-WH SST31LF041A-300-4E-WH SST31LF043 Valid combinations SST31LF043-70-4C-WI SST31LF043-70-4E-WI SST31LF043A Valid combinations SST31LF043A-300-4C-WH SST31LF043A-300-4E-WH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 23 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet PACKAGING DIAGRAMS Pin # 1 Identifier 1.05 0.95 .50 BSC 8.10 7.90 .270 .170 12.50 12.30 0.15 0.05 0.70 0.50 14.20 13.80 32.TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH X 14MM (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 24 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet Pin # 1 Identifier 1.05 0.95 .50 BSC .270 .170 10.10 9.90 12.50 12.30 0.15 0.05 0.60 0.40 14.20 13.80 40.TSOP-WI-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 CA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM SST PACKAGE CODE: WI X 14MM (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 25 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A Data Sheet Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com (c)2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 26 |
Price & Availability of SST31LF043A-70-4C-WI
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